Resin的安装和配置 Resin 可以在 http://www.caucho.com/download/index.xtp免费下载和使用。使用Res in开发或者学习是免 费的,
标签: Resin download caucho index
上传时间: 2014-01-10
上传用户:leehom61
系统构架师论文论文 系统构架师论文论文 系统构架师论文论文 系统构架师论文论文系统构架师论文论文https://www.eeworm.com/dl/617/195136.htmlhttps://www.eeworm.com/dl/617/195136.html
上传时间: 2021-10-18
上传用户:陈浩
pubwin2007此工具是必须结合文章 Pubwin2007破解全攻略(http://www.netbarghost.com/wpaper/03/01.html) 使用 网吧幽灵(http://www.netbarghost.com)
标签: 2007 http netbarghost pubwin
上传时间: 2013-12-17
上传用户:lx9076
登录器源码 登录器源码 登录器源码 登录器源码 登录器源码 登录器源码 登录器源码 登录器源码
标签: 登录器源码登录器源码
上传时间: 2015-06-04
上传用户:wdf100
库存管理系统
标签: 库存管理系统
上传时间: 2016-05-09
上传用户:ccn158525
cardoso的独立分量分析(ICA)的特征矩阵联合近似对角化(JADE)方法。
标签: JADE
上传时间: 2017-05-08
上传用户:1044109363@qq.com
PCI插槽64位板卡 转换座的pcb和原理图
上传时间: 2019-10-09
上传用户:zhmy923
中文版详情浏览:http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
标签: UltraScale Xilinx 架构
上传时间: 2013-11-21
上传用户:wxqman
这一节的目的是使用XPS为ARM PS 处理系统 添加额外的IP。从IP Catalog 标签添加GPIO,并与ZedBoard板子上的8个LED灯相连。当系统建立完后,产生bitstream,并对外设进行测试。本资料为源代码,原文设计过程详见:【 玩转赛灵思Zedboard开发板(4):如何使用自带外设IP让ARM PS访问FPGA?】 硬件平台:Digilent ZedBoard 开发环境:Windows XP 32 bit 软件: XPS 14.2 +SDK 14.2
上传时间: 2013-11-06
上传用户:yuchunhai1990
电子发烧友网:针对目前电子发烧友网举办的“玩转FPGA:iPad2,赛灵思开发板等你拿”,小编在电话回访过程中留意到有很多参赛选手对Xilinx 公司的FPGA及其设计流程不是很熟悉,所以特意在此整理了一些相关知识,希望对大家有所帮助。当然也希望Xilinx FPGA爱好者能跟我们一起来探讨学习! 本文主要帮助大家熟悉利用ISE进行Xilinx 公司FPGA 代码开发的基本流程。主要是帮助初学者了解和初步掌握 ISE 的使用,不需要 FPGA 的开发基础,所以对每个步骤并不进行深入的讨论。 图 实例显示成果图
上传时间: 2013-10-16
上传用户:脚趾头